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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
Integrated Device Technology, Inc.
IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT
FEATURES:
* Common features: - Low input and output leakage 1A (max.) - CMOS power levels - True TTL input and output compatibility - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) - Meets or exceeds JEDEC standard 18 specifications - Product available in Radiation Tolerant and Radiation Enhanced versions - Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) - Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages * Features for FCT821T/FCT823T/FCT825T: - A, B, C and D speed grades - High drive outputs (-15mA IOH, 48mA IOL) - Power off disable outputs permit "live insertion"
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal CMOS technology. The FCT82xT series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T are buffered, 10-bit wide versions of the popular FCT374T function. The FCT823T are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) - ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT825T are 8-bit buffered registers with all the FCT823T controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring high IOL/IOH. The FCT82xT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0 EN
DN
CLR D CL Q D CL Q
CP Q
CP Q
CP
OE Y0 YN
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc
AUGUST 1995
DSC-4202/5
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
D8 D9 GND NC CP Y9 Y8
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND
1 2 3 4 P24-1 5 D24-1 6 SO24-2 7 SO24-7 SO24-8 8 & 9 E24-1 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CP
D2 D3 D4 NC D5 D6 D7
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18
D1 D0 OE NC VCC Y0 Y1
FCT821 10-BIT REGISTER
Y2 Y3 Y4 NC Y5 Y6 Y7
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DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
D8 CLR GND NC CP EN
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND
1 2 3 P24-1 4 D24-1 5 SO24-2 6 SO24-7 7 SO24-8 8 & 9 E24-1 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 EN CP
D2 D3 D4 NC D5 D6 D7
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18
Y8
D1 D0 OE NC VCC Y0 Y1
FCT823 9-BIT REGISTER
INDEX
Y2 Y3 Y4 NC Y5 Y6 Y7
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DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
FCT825 8-BIT REGISTER
INDEX OE1 OE2 D0 D1 D2 D3 D4 D5 D6 D7 CLR GND 24 1 23 2 22 3 4 P24-1 21 5 D24-1 20 6 SO24-2 19 7 SO24-8 18 & 17 8 E24-1 16 9 10 15 14 11 12 13 VCC OE3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 EN CP
D0 OE2 OE1 NC VCC OE3 Y0
D1 D2 D3 NC D4 D5 D6
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18
D7 CLR GND NC CP EN Y7
Y1 Y2 Y3 NC Y4 Y5 Y6
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DIP/SOIC/QSOP/CERPACK TOP VIEW
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LCC TOP VIEW
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Names DI
CLR
FUNCTION TABLE(1)
Inputs
OE CLR EN
I/O I I
Description The D flip-flop data inputs. When the clear input is LOW and OE is LOW, the QI outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into the register on the LOW-toHIGH transition. The register 3-state outputs. Clock Enable. When the clock enable is LOW, data on the D I input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the Y I outputs are in the highimpedance state. When the OE input is LOW, the TRUE register data is present at the YI outputs.
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DI L H X X X X L H L H
CP X X X X
Internal/ Outputs QI YI L H L L NC NC L H L H Z Z Z L Z NC Z Z L H
H H H L H L H H L L
H H L L H H H H H H
L L X X H H L L L L
Function High Z Clear Hold Load
CP
I
YI
EN
O I
OE
I
NOTE: 1. H = HIGH L = LOW X = Don't Care NC = No Change = LOW-to-HIGH Transition Z = High Impedance
2567 tbl 02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial (2) Terminal Voltage VTERM -0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage -0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature -55 to +125 Under Bias TSTG Storage -55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current -60 to +120 Military -0.5 to +7.0 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
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-0.5 to VCC +0.5 -55 to +125 -65 to +135 -65 to +150 0.5 -60 to +120
V C C C W mA
NOTE: 1. This parameter is measured at characterization but not tested.
2567 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Input LOW Current (4) Current (4) VCC = Max. pins) (4) VCC = Min., IIN = -18mA
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V VCC = Max., VI = VCC (Max.)
Min. 2.0 -- -- -- -- -- -- -- -- --
Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01
Max. -- 0.8
Unit V V
1 1 1 1 1
-1.2 -- 1
A A A
V mV mA
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High Impedance Output Current (3-State Output Input HIGH Current (4)
Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
OUTPUT DRIVE CHARACTERISTICS FOR FCT821/823/825T
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min. IOH = -6mA MIL. VIN = VIH or VIL IOH = -8mA COM'L. IOH = -12mA MIL. IOH = -15mA COM'L. VCC = Min. IOL = 32mA MIL. VIN = VIH or VIL IOL = 48mA COM'L. VCC = Max., VO = GND (3) Leakage(5) VCC = 0V, VIN or VO 4.5V Min. 2.4 2.0 -- -60 -- Typ.(2) 3.3 3.0 0.3 -120 -- Max. -- -- 0.5 -225 1 Unit V V V mA A
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VOL IOS IOFF
Output LOW Voltage Short Circuit Current Input/Output Power Off
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = EN = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle OE = EN = GND One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle OE = EN = GND Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle Min. -- VIN = VCC VIN = GND -- Typ.(2) 0.5 0.15 Max. 2.0 0.25 Unit mA mA/ MHz
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND
--
1.5
3.5
mA
VIN = 3.4V VIN = GND
--
2.0
5.5
VIN = VCC VIN = GND
--
3.8
7.3 (5)
VIN = 3.4V VIN = GND
--
6.0
16.3 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825AT Com'l. Symbol tPLH tPHL Parameter
Propagation Delay CP to YI (OE = LOW)
FCT821/823/825BT Com'l. Min.(2) 1.5 1.5 3.0 1.5 3.0 0 1.5 6.0 6.0 6.0 1.5 1.5 1.5 1.5 Max. 7.5 15.0 -- -- -- -- 9.0 -- -- -- 8.0 15.0 6.5 7.5 1.5 1.5 3.0 1.5 3.0 0 1.5 6.0 6.0 6.0 1.5 1.5 1.5 1.5 Mil. Min. (2) Max. 8.5 16.0 -- -- -- -- 9.5 -- -- -- 9.0 16.0 7.0 8.0
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Mil. Min.(2) 1.5 1.5 4.0 2.0 4.0 2.0 1.5 7.0 7.0 7.0 1.5 1.5 1.5 1.5 Max. 11.5 20.0 -- -- -- -- 15.0 -- -- -- 13.0 25.0 8.0 9.0
Condition(1) CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500
Min.(2) 1.5 1.5 4.0 2.0 4.0 2.0 1.5 6.0 7.0 6.0
Max. 10.0 20.0 -- -- -- -- 14.0 -- -- -- 12.0 23.0 7.0 8.0
Unit ns
tSU tH tSU tH tPHL tREM tW tW tPZH tPZL
Set-up Time HIGH or LOW DI to CP Hold Time HIGH or LOW DI to CP Set-up Time HIGH or LOW EN to CP Hold Time HIGH or LOW EN to CP Propagation Delay, CLR to YI Recovery Time CLR to CP Clock Pulse Width HIGH or LOW
CLR
ns ns ns ns ns ns ns ns ns
Pulse Width LOW
Output Enable Time OE to YI
tPHZ tPLZ
Output Disable Time OE to Y I
CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 5pF(4) RL = 500 CL = 50pF RL = 500
1.5 1.5 1.5 1.5
ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. This condition is guaranteed but not tested.
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825CT Com'l. Symbol tPLH tPHL Parameter
Propagation Delay CP to YI (OE = LOW)
FCT823DT Com'l. Min.(2) 1.5 1.5 2.0 1.0 3.0 0 1.5 3.0 3.0 3.0 1.5 1.5 1.5 1.5 Max. 5.0 8.5 -- -- -- -- 5.0 -- -- -- 4.8 9.0 4.0 4.0
2567 tbl 09
Mil. Min.(2) 1.5 1.5 3.0 1.5 3.0 0 1.5 6.0 6.0 6.0 1.5 1.5 1.5 1.5 Max. 7.0 13.5 -- -- -- -- 8.5 -- -- -- 8.0 13.5 6.0 6.5
Condition(1) CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500
Min.(2) 1.5 1.5 3.0 1.5 3.0 0 1.5 6.0 6.0 6.0
Max. 6.0 12.5 -- -- -- -- 8.0 -- -- -- 7.0 12.5 6.0 6.5
Unit ns
tSU tH tSU tH tPHL tREM tW tW tPZH tPZL
Set-up Time HIGH or LOW DI to CP Hold Time HIGH or LOW DI to CP Set-up Time HIGH or LOW EN to CP Hold Time HIGH or LOW EN to CP Propagation Delay, CLR to YI Recovery Time CLR to CP Clock Pulse Width HIGH or LOW(3)
CLR
ns ns ns ns ns ns ns ns ns
Pulse Width LOW(3)
Output Enable Time OE to YI
tPHZ tPLZ
Output Disable Time OE to Y I
CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 5pF(4) RL = 500 CL = 50pF RL = 500
1.5 1.5 1.5 1.5
ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. This condition is guaranteed but not tested.
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
2567 lnk 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Switch
Closed
2567 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2567 drw 06
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2567 drw 07
tSU
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V
2567 drw 09
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2567 drw 08
CONTROL INPUT tPLZ
0V 3.5V 0.3V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX Temp. Range XXXX Device Type X Package X Process Blank B P D E L SO PY Q 821AT 823AT 825AT 821BT 823BT 825BT 821CT 823CT 825CT 823DT Commercial MIL-STD-883, Class B Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package 10-Bit Non-Inverting Register 9-Bit Non-Inverting Register 8-Bit Non-Inverting Register
54 74
-55C to +125C 0C to +70C
2567 drw 10
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